With improvements in the performance of communication backbone devices or information processing devices such as servers, the communication speed inside and outside devices is increased. In order to recover signals that have degraded in transmission lines, a clock data recovery (CDR) circuit is disposed in a reception circuit that receives signals communicated at high speed.
The related art is disclosed in Japanese National Publication of International Patent Application No. 2000-515337, A. Pottbacker, et al., “A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s”, JSSC, VOL. 27, NO. 12, pp. 1747-1751, December 1992, or Behzad Razavi, Design of Integrated Circuits for Optical Communications, p. 217, Sep. 12, 2002.